1. Field of the Invention
The present invention relates to a field effect transistor and a method of manufacturing the same and, more particularly, to a high-transconductance, high-performance field effect transistor and a method of manufacturing the same.
2. Description of the Prior Art
FIG. 1 shows the section of one structure of a conventional field effect transistor. As shown in FIG. 1, this structure is obtained by sequentially forming a 10-nm thick undoped GaAs buffer layer 32, a 10-nm thick undoped In.sub.0.25 Ga.sub.0.75 As channel layer 33, a 25-nm thick Si-doped n-type In.sub.0.48 Ga.sub.0.52 P electron donor layer 34 (n=2.times.10.sup.18 cm.sup.-3), and a Si-doped n-type GaAs cap layer 36 (n=2.times.10.sup.18 cm.sup.-3) on a GaAs substrate 31. In this structure, the two-dimensional sheet electron dose and mobility at room temperature are 1.4 to 1.5.times.10.sup.12 cm.sup.-2 and 7,000 cm.sup.2 /V sec, respectively.
As the gate electrode formation process, a photoresist is applied to an oxide film (Sio.sub.2), and a pattern is formed by electron beam exposure. A gate pattern is formed on the oxide film by reactive ion etching. Subsequently, using this oxide film as a mask, the GaAs cap layer 36 is etched by selective dry etching to reach the In.sub.0.48 Ga.sub.0.52 P electron donor layer 34, thereby forming a recess. After that, WSi Schottky gate metal is formed by sputtering, and Au is formed by vapor deposition. Unnecessary gate metal is removed to form a gate electrode.
AuGe/Ni/Au is formed by vapor deposition to form ohmic electrodes, i.e., a source electrode 37 and a drain electrode 38.
Finally, an SiO.sub.2 /SiN passivation film is formed to obtain a conventional field effect transistor.
According to the characteristics of this conventional field effect transistor, when the transistor has a maximum transconductance gmmax of about 480 mS/mm, a gate-to-drain breakdown voltage BVgd of 7 V or more, and a gate width of 200 .mu.m, a maximum oscillation frequency fmax is 191 GHz, and a cutoff frequency fT is 76 GHz. These figures are described in IEEE ELECTRON DEVICE LETTERS, VOL. 14, NO. 8, pp. 406-408 (1993).
As a reference that describes conditions for the crystal growth of the conventional field effect transistor described above, Journal of Crystal Growth, vol. 107, pp. 942-946 (1991) is cited. According to this reference, crystal growth is performed by setting the reaction tube pressure to normal pressure and setting the growing temperature to 630.degree. C.
Japanese Unexamined Patent Publication No. 8-306703 and the like describe a compound semiconductor crystal device and a method of manufacturing the same.
The above references concerning the conventional field effect transistor have no description on the direction of the gate finger of the FET and the practical growth conditions for the In.sub.0.48 Ga.sub.0.52 P electron donor layer 34, which forms an interface together with the In.sub.0.25 Ga.sub.0.75 As channel layer 33 and in which the array of Ga and In layers, i.e., natural superlattice formation state changes depending on the growing temperature, the V/III ratio, the growing rate, and the substrate plane orientation.
In a field effect transistor (FET) using InGaAs as a channel layer, the state of interface between the channel layer and the electron donor layer formed on the channel layer largely affects the mobility of the two-dimensional electron gas. In particular, in an FET having a crystal structure in which InGaP is formed on an InGaAs channel layer as an electron donor layer, the degree of formation of the natural superlattice in the InGaP electron donor layer changes largely depending on the growth conditions for the InGaP crystals. The mobility of the two-dimensional electron gas accordingly changes largely depending on the degree of formation of the natural superlattice.
Depending on the degree of formation of the natural superlattice in the InGaP electron donor layer and the direction of the gate finger, electrons traveling in the channel layer scatter largely to decrease the mobility of the two-dimensional electron gas, and the FET performance that should naturally be obtained cannot be sufficiently obtained.